The present invention relates generally to the field of statistical timing analysis and more particularly to computing the expected timing of a digital circuit.
In integrated circuit design, timing closure is a complex issue. Static timing analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation. High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate. Gauging the ability of a circuit to operate at the specified speed requires ability to measure, during the design process, its delay at numerous steps. Moreover, delay calculation must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (placement and routing), optimizations performed late in the design cycle.
While such timing measurements can theoretically be performed using a rigorous circuit simulation, such an approach is liable to be too slow to be practical. Static timing analysis uses simplified delay models to provide a timely and reasonably accurate measurement of circuit timing. Static timing analysis also uses simplified delay models because of the ability of static timing analysis to consider the effects of logical interactions between signals is limited. Nevertheless, it has become a mainstay of circuit design over the last few decades.